6 search results - page 1 / 2 » Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Gene... |
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
JOLPE
2008
13 years 4 months ago
2008
DAC
2007
ACM
14 years 5 months ago
2007
ACM
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
In this paper, we propose a new circuit transformation technique in conjunction with the use of a special diagnostic test pattern, named SO-SLAT pattern, to achieve higher multipl...
VTS
2007
IEEE
13 years 11 months ago
2007
IEEE
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...