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» Limitations of self-assembly at temperature 1
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DNA
2008
Springer
104views Bioinformatics» more  DNA 2008»
13 years 6 months ago
Self-assembly of Discrete Self-similar Fractals
In this paper, we search for theoretical limitations of the Tile Assembly Model (TAM), along with techniques to work around such limitations. Specifically, we investigate the self...
Matthew J. Patitz, Scott M. Summers
DAC
2007
ACM
14 years 5 months ago
Placement of 3D ICs with Thermal and Interlayer Via Considerations
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...
Brent Goplen, Sachin S. Sapatnekar
ASPDAC
2012
ACM
241views Hardware» more  ASPDAC 2012»
12 years 15 days ago
Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems
Abstract— Integrating optical interconnects into the nextgeneration multi-/many-core architecture has been considered a viable solution to addressing the limitations in throughpu...
Yan Zheng, Peter Lisherness, Saeed Shamshiri, Amir...
FOCS
1993
IEEE
13 years 9 months ago
Simulated Annealing for Graph Bisection
We resolve in the a rmative a question of Boppana and Bui: whether simulated annealing can, with high probability and in polynomial time, nd the optimal bisection of a random grap...
Mark Jerrum, Gregory B. Sorkin
DFT
2006
IEEE
105views VLSI» more  DFT 2006»
13 years 10 months ago
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinge...