In this paper, we search for theoretical limitations of the Tile Assembly Model (TAM), along with techniques to work around such limitations. Specifically, we investigate the self...
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...
Abstract— Integrating optical interconnects into the nextgeneration multi-/many-core architecture has been considered a viable solution to addressing the limitations in throughpu...
Yan Zheng, Peter Lisherness, Saeed Shamshiri, Amir...
We resolve in the a rmative a question of Boppana and Bui: whether simulated annealing can, with high probability and in polynomial time, nd the optimal bisection of a random grap...
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinge...