22 search results - page 4 / 5 » LogTM-SE: Decoupling Hardware Transactional Memory from Cach... |
MICRO
2010
IEEE
13 years 3 months ago
2010
IEEE
Abstract--Many shared-memory parallel systems use lockbased synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are i...
ISCA
1995
IEEE
13 years 8 months ago
1995
IEEE
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
IEEEPACT
2005
IEEE
13 years 11 months ago
2005
IEEE
Transactional Coherence and Consistency (TCC) is a novel coherence scheme for shared memory multiprocessors that uses programmer-defined transactions as the fundamental unit of p...
MICRO
2008
IEEE
13 years 5 months ago
2008
IEEE
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
HPCA
2011
IEEE
12 years 9 months ago
2011
IEEE
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...