35 search results - page 5 / 7 » Loop Scheduling and Partitions for Hiding Memory Latencies |
DATE
2009
IEEE
14 years 12 days ago
2009
IEEE
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
JSSPP
2004
Springer
13 years 11 months ago
2004
Springer
Job scheduling typically focuses on the CPU with little work existing to include I/O or memory. Time-shared execution provides the chance to hide I/O and long-communication latenc...
ISCA
2010
IEEE
13 years 10 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
ICCAD
2003
IEEE
14 years 2 months ago
2003
IEEE
— Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latenc...
TVLSI
2008
13 years 5 months ago
2008
This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...