22 search results - page 2 / 5 » Loop Transformations for Architectures with Partitioned Regi... |
IPPS
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents results on a new approach to partitioning a modulo-scheduled loop for distributed execution on parallel clusters of functional units organized as a VLIW machin...
MICRO
2000
IEEE
13 years 5 months ago
2000
IEEE
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
The Discrete Wavelet Transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall ...
ICCD
2000
IEEE
14 years 2 months ago
2000
IEEE
We introduce a new register file architecture that provides both row-wise and column-wise accesses, thus allowing partitioned instructions to be used in columnwise processing with...
FPL
2009
Springer
13 years 9 months ago
2009
Springer
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...