20 search results - page 4 / 4 » Low Latency, High Throughput, and Less Complex VLSI Architec... |
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
MICRO
2009
IEEE
13 years 12 months ago
2009
IEEE
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
MICRO
2008
IEEE
13 years 11 months ago
2008
IEEE
As companies move towards many-core chips, an efficient onchip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scala...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
OTM
2009
Springer
13 years 12 months ago
2009
Springer
Complex event processing (CEP) is a software architecture paradigm that aims at low latency, high throughput, and quick adaptability of applications for supporting and improving ev...