26 search results - page 1 / 6 » Low Power Oriented CMOS Circuit Optimization Protocol |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
IWSOC
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper explores the design and optimization of Quasi-Floating Gate MOS techniques to lowvoltage/low-power digital circuitry. The simulated power consumption of standard CMOS g...
ISLPED
1999
ACM
13 years 9 months ago
1999
ACM
The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1V and threshold voltage as low as 0.2V ...
ICCAD
1993
IEEE
13 years 9 months ago
1993
IEEE
ISVLSI
2002
IEEE
13 years 9 months ago
2002
IEEE
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits ha...