26 search results - page 2 / 6 » Low Power Oriented CMOS Circuit Optimization Protocol |
ICCAD
1996
IEEE
13 years 9 months ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
VLSID
2001
IEEE
14 years 5 months ago
2001
IEEE
Development of the process technology for dual threshold (dual Vth ) CMOS circuit has opened up the possibility of using it to reduce static power in low voltage high performance ...
ISLPED
1997
ACM
13 years 8 months ago
1997
ACM
In this paper we report the fully depleted CMOS/SOI device design guidelines for low power applications. Optimal technology, device and circuit parameters are discussed and compar...
AUTOID
2005
IEEE
13 years 11 months ago
2005
IEEE
This paper presents a novel low power and high performance analog front end circuit for passive RFID transponder. With a novel architecture including three rectifier circuits, amo...
ASPDAC
2009
ACM
13 years 10 months ago
2009
ACM
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise pro...