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» Low power SRAM techniques for handheld products
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ISLPED
2005
ACM
68views Hardware» more  ISLPED 2005»
13 years 10 months ago
Low power SRAM techniques for handheld products
SRAM leakage constitutes a significant portion of the standby power budget of modern SoC products for handheld applications such as PDA and cellular phones. NMOS and PMOS reverse ...
Rabiul Islam, Adam Brand, Dave Lippincott
ISQED
2008
IEEE
120views Hardware» more  ISQED 2008»
13 years 11 months ago
Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation
We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SR...
Huifang Qin, Animesh Kumar, Kannan Ramchandran, Ja...
ISQED
2010
IEEE
170views Hardware» more  ISQED 2010»
13 years 6 months ago
New SRAM design using body bias technique for ultra low power applications
A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering ...
Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Yn...
JSA
2000
96views more  JSA 2000»
13 years 4 months ago
Design techniques for low-power systems
Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low power d...
Paul J. M. Havinga, Gerard J. M. Smit
ISCAS
2007
IEEE
132views Hardware» more  ISCAS 2007»
13 years 11 months ago
High Read Stability and Low Leakage Cache Memory Cell
- Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct access to the data storage nodes through the bit lines...
Zhiyu Liu, Volkan Kursun