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VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
13 years 11 months ago
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
Sanjeev K. Jain, Pankaj Agarwal
GLVLSI
2007
IEEE
134views VLSI» more  GLVLSI 2007»
14 years 3 days ago
Sleep transistor distribution in row-based MTCMOS designs
- The Multi-Threshold CMOS (MTCMOS) technology has become a popular technique for standby power reduction. This technology utilizes high-Vth sleep transistors to reduce subthreshol...
Chanseok Hwang, Peng Rong, Massoud Pedram
VLSISP
2010
148views more  VLSISP 2010»
13 years 4 months ago
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive
Abstract Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementatio...
Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunso...
GLVLSI
2006
IEEE
110views VLSI» more  GLVLSI 2006»
13 years 12 months ago
Synthesis of a wideband low noise amplifier
Two generations of a wideband low noise amplifier (LNA) employing noise canceling principle have been synthesized. The first generation design was fabricated in a 0.35 µm SiGe Bi...
Abhishek Jajoo, Michael Sperling, Tamal Mukherjee
VLSID
2002
IEEE
131views VLSI» more  VLSID 2002»
14 years 6 months ago
Divide-and-Conquer IDDQ Testing for Core-Based System Chips
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
C. P. Ravikumar, Rahul Kumar