45 search results - page 1 / 9 » Low power techniques for address encoding and memory allocat... |
ASPDAC
2001
ACM
13 years 8 months ago
2001
ACM
- This paper presents encoding techniques to optimize the switching activity on a multiplexed DRAM address bus. The DRAM switching activity can be classified either as external (be...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
Abstract— The memory subsystem is known to comprise a significant fraction of the power dissipation in embedded systems. The memory addressing strategy, which determines the seq...
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
This paper proposes a data encoder to reduce switched capacitance on system bus. Our method focuses on transferring raw video data (pixels) between off-chip memory and on-chip mem...
VLSID
2003
IEEE
14 years 5 months ago
2003
IEEE
The working-zone encoding (WZE) method employing locality of memory reference was previously proposed to reduce address bus switching activity. This paper presents an encoding met...
WMPI
2004
ACM
13 years 10 months ago
2004
ACM
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...