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» Low- and Ultra Low-Power Arithmetic Units: Design and Compar...
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ICCD
2005
IEEE
111views Hardware» more  ICCD 2005»
14 years 1 months ago
Low- and Ultra Low-Power Arithmetic Units: Design and Comparison
Design guidelines for low- and ultra low-power arithmetic units are presented. We analyze structures for addition in the energy-delay space to determine the most suitable for thes...
Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdz...
ICMCS
2005
IEEE
123views Multimedia» more  ICMCS 2005»
13 years 10 months ago
Nearly Lossless Content-Dependent Low-Power DCT Design for Mobile Video Applications
This paper proposes a practical content-dependent lowpower DCT design with tolerable quality drop. Lowpower issue has become more and more important, especially for portable devic...
Chia-Ping Lin, Po-Chih Tseng, Liang-Gee Chen
ERSA
2006
99views Hardware» more  ERSA 2006»
13 years 6 months ago
Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC)
- This paper presents the design and implementation methodology of some low power programmable FIR filtering IP cores targeting SoRC and compares their performance in term of area,...
Muhammad Akhtar Khan, Abdul Hameed, Ahmet T. Erdog...
ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
13 years 7 months ago
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
Swaroop Ghosh, Kaushik Roy
GLVLSI
2003
IEEE
152views VLSI» more  GLVLSI 2003»
13 years 10 months ago
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
Frank Grassert, Dirk Timmermann