18 search results - page 1 / 4 » Lowering Power Consumption in Clock by Using Globally Asynch... |
DAC
1999
ACM
13 years 9 months ago
1999
ACM
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
ISCA
2002
IEEE
13 years 9 months ago
2002
IEEE
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
DAC
2007
ACM
14 years 5 months ago
2007
ACM
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...