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» MIST - A Design Aid for Programmable Pipelined Processors
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GLVLSI
2006
IEEE
95views VLSI» more  GLVLSI 2006»
13 years 11 months ago
Test generation using SAT-based bounded model checking for validation of pipelined processors
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
Heon-Mo Koo, Prabhat Mishra
CODES
2008
IEEE
13 years 7 months ago
Specification-based compaction of directed tests for functional validation of pipelined processors
Functional validation is a major bottleneck in microprocessor design methodology. Simulation is the widely used method for functional validation using billions of random and biase...
Heon-Mo Koo, Prabhat Mishra
DAC
1999
ACM
14 years 6 months ago
LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures
Abstract { This paper presents the machine description language LISA for the generation of bitand cycle accurate models of DSP processors. Based on a behavioral operation descripti...
Stefan Pees, Andreas Hoffmann, Vojin Zivojnovic, H...
DAC
2010
ACM
13 years 5 months ago
Automatic multithreaded pipeline synthesis from transactional datapath specifications
We present a technique to automatically synthesize a multithreaded in-order pipeline from a high-level unpipelined datapath specification. This work extends the previously propose...
Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timo...
DAC
2006
ACM
14 years 6 months ago
Synthesis of high-performance packet processing pipelines
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards