12 search results - page 2 / 3 » Mapping DSP Applications to a High-Performance Reconfigurabl... |
ESTIMEDIA
2007
Springer
13 years 8 months ago
2007
Springer
Due to the increasing demands on efficiency, performance and flexibility reconfigurable computational architectures are very promising candidates in embedded systems design. Recent...
APCSAC
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper introduces a method which can be used to map applications written in a high level source language program, like C, to a coarse grain reconfigurable architecture, MONTIU...
VLSISP
2008
13 years 4 months ago
2008
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
ASAP
2005
IEEE
13 years 10 months ago
2005
IEEE
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
IPPS
2006
IEEE
13 years 10 months ago
2006
IEEE
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...