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» Mapping between Levels in the Metamodel Architecture
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ISCA
2009
IEEE
148views Hardware» more  ISCA 2009»
14 years 19 days ago
Memory mapped ECC: low-cost error protection for last level caches
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
Doe Hyun Yoon, Mattan Erez
SEKE
2007
Springer
14 years 3 days ago
A Model-driven Approach to Architecting Secure Software
A software architecture provides a high-level description of a software solution in terms of the structure, topology, and interactions between its principal components. While a nu...
Ebenezer A. Oladimeji, Sam Supakkul, Lawrence Chun...
FDL
2007
IEEE
14 years 10 days ago
Mapping Actor-Oriented Models to TLM Architectures
Actor-oriented modeling approaches are convenient for implementing functional models of embedded systems. Architectural models for heterogeneous system-on-chip architectures, howe...
Jens Gladigau, Christian Haubelt, Bernhard Niemann...
ISCA
1998
IEEE
145views Hardware» more  ISCA 1998»
13 years 10 months ago
Multi-Level Texture Caching for 3D Graphics Hardware
Traditional graphics hardware architectures implement what we call the push architecture for texture mapping. Local memory is dedicated to the accelerator for fast local retrieval...
Michael Cox, Narendra Bhandri, Michael Shantz
DATE
2004
IEEE
158views Hardware» more  DATE 2004»
13 years 9 months ago
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the e...
Srinivasan Murali, Giovanni De Micheli