4 search results - page 1 / 1 » Mapping the LU decomposition on a many-core architecture: ch... |
CF
2009
ACM
13 years 11 months ago
2009
ACM
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
EUROPAR
2010
Springer
13 years 5 months ago
2010
Springer
Abstract. Performance of the on-chip cache is critical for processor. The multithread program model usually employed by on-chip many-core architectures may have effects on cache ac...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
In this paper, we investigate the core-switch mapping(CSM) problem that optimally maps cores onto an NoC architecture such that either the energy consumption or the congestion is ...
DAC
2009
ACM
14 years 5 months ago
2009
ACM
In double patterning lithography (DPL), coloring conflict and stitch minimization are the two main challenges. Post layout decomposition algorithm [1] [2]may not be enough to achi...