26 search results - page 3 / 6 » Maximizing Performance by Retiming and Clock Skew Scheduling |
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock ...
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
As the minimum feature sizes of VLSI circuits get smaller while the clock frequency increases, the effects of process variations become significant. We propose a UST/DME based ap...
DATE
2009
IEEE
14 years 15 days ago
2009
IEEE
- Clock skew scheduling (CSS) is an effective technique to optimize clock period of sequential designs. However, these techniques are not effective in the presence of certain desig...
DAC
2008
ACM
13 years 7 months ago
2008
ACM
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
ICCD
2004
IEEE
14 years 2 months ago
2004
IEEE
Potential slack is an effective metric of circuit’s possible performance improvement. It is equal to the maximal amount of slack that can be potentially used for optimization. I...