180 search results - page 1 / 36 » Measuring routing congestion for multi-layer global routing |
DAC
1998
ACM
14 years 6 months ago
1998
ACM
In this paper we present a new global router appropriate for Multichip Module MCM and dense Printed Circuit Board PCB design, which utilizes a hybrid of the classical rip-up and r...
GLVLSI
2000
IEEE
13 years 9 months ago
2000
IEEE
DAC
2000
ACM
14 years 6 months ago
2000
ACM
FPGA routing resources typically consist of segments of various lengths. Due to the segmented routing architectures, the traditional measure of wiring cost (wirelength, delay, con...
TCAD
2010
12 years 12 months ago
2010
Global routing for modern large-scale circuit designs has attracted much attention in the recent literature. Most of the state-of-the-art academic global routers just work on a sim...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...