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» Memory Estimation for High Level Synthesis
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DAC
1994
ACM
13 years 8 months ago
Memory Estimation for High Level Synthesis
Abstract -- This paper describes a new memory estimation technique for DSP applications written in an applicative language. Since no concept of storage is present in an applicative...
Ingrid Verbauwhede, Chris J. Scheers, Jan M. Rabae...
CORR
2006
Springer
116views Education» more  CORR 2006»
13 years 4 months ago
Memory Aware High-Level Synthesis for Embedded Systems
We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory...
Gwenolé Corre, Eric Senn, Nathalie Julien, ...
DSD
2010
IEEE
162views Hardware» more  DSD 2010»
13 years 3 months ago
A Parallel for Loop Memory Template for a High Level Synthesis Compiler
—We propose a parametrized memory template for applications with parallel for loops. The template’s parameters reflect important trade-offs made during system design. The temp...
Craig Moore, Wim Meeus, Harald Devos, Dirk Strooba...
ISSS
2002
IEEE
176views Hardware» more  ISSS 2002»
13 years 9 months ago
Controller Estimation for FPGA Target Architectures during High-Level Synthesis
In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence,...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...
ISSS
2000
IEEE
127views Hardware» more  ISSS 2000»
13 years 9 months ago
Lower Bound Estimation for Low Power High-Level Synthesis
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Sta...