354 search results - page 1 / 71 » Memory and compiler optimizations for low-power and -energy |
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e.,...
GLVLSI
2008
IEEE
2008
IEEE
Simultaneous optimization of memory configuration and code allocation for low power embedded systems
13 years 5 months ago
This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low Vdd and Vth and 2) a static power ...
ICCD
2001
IEEE
14 years 1 months ago
2001
IEEE
Lowering power consumption in microprocessors, whether used in portables or not, has now become one of the most critical design concerns. On-chip cache memories tend to occupy dom...
ASPDAC
2001
ACM
13 years 8 months ago
2001
ACM
- This paper presents encoding techniques to optimize the switching activity on a multiplexed DRAM address bus. The DRAM switching activity can be classified either as external (be...
HOTI
2008
IEEE
13 years 11 months ago
2008
IEEE
Several types of low power passive equalizer is proposed and optimized in this work. The equalizer topologies include T-junction, parallel R-C and series R-L structures. These str...