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ARC
2010
Springer
167views Hardware» more  ARC 2010»
13 years 9 months ago
Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures
Coarse Grained Reconfigurable Array (CGRA) architectures give high throughput and data reuse for regular algorithms while providing flexibility to execute multiple algorithms on th...
Kunjan Patel, Chris J. Bleakley
FPL
2004
Springer
122views Hardware» more  FPL 2004»
13 years 11 months ago
Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path
A high-performance reconfigurable coarse-grain data-path, part of a hybrid reconfigurable platform, is introduced. The data-path consists of coarse grain components that their flex...
Michalis D. Galanis, George Theodoridis, Spyros Tr...
IPPS
2005
IEEE
13 years 11 months ago
A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures
This paper presents a compiler methodology for memoryaware mapping on 2-Dimensional coarse-grained reconfigurable architectures that aims in improving the mapped applications’ p...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
ERSA
2009
146views Hardware» more  ERSA 2009»
13 years 3 months ago
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor
We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...
Wim Vanderbauwhede, Martin Margala, Sai Rahul Chal...
FPL
2009
Springer
113views Hardware» more  FPL 2009»
13 years 10 months ago
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays
Spatially-tiled architectures, such as Coarse-Grained Reconfigurable Arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, em...
Brian Van Essen, Aaron Wood, Allan Carroll, Stephe...