14 search results - page 1 / 3 » Methodologies and Algorithms for Testing Switch-Based NoC In... |
DFT
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper, we present two novel methodologies for testing the interconnect fabrics of network-on-chip (NoC) based chips. Both use the concept of recursive testing, with differ...
DSD
2006
IEEE
13 years 11 months ago
2006
IEEE
Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when th...
ASAP
2007
IEEE
13 years 5 months ago
2007
IEEE
Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single system on chip (SoC) currently, and the number is likely to increase significa...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
1 This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the ...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...