Methodologies and Algorithms for Testing Switch-Based NoC Interconnects

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In this paper, we present two novel methodologies for testing the interconnect fabrics of network-on-chip (NoC) based chips. Both use the concept of recursive testing, with different degrees of parallelism in each case. Our test methodologies cover the logic switching blocks and the FIFO buffers that are the basic components of NoC fabrics. The paper concludes with test time evaluations for different NoC topologies and sizes.

Cristian Grecu, Partha Pratim Pande, Baosheng Wang

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DFT 2005 | Hardware | Logic Switching Blocks | NoC Fabrics | Test Time Evaluations |

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Added	24 Jun 2010
Updated	24 Jun 2010
Type	Conference
Year	2005
Where	DFT
Authors	Cristian Grecu, Partha Pratim Pande, Baosheng Wang, André Ivanov, Res Saleh

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Methodologies and Algorithms for Testing Switch-Based NoC Interconnects

DFT 2005 | Hardware | Logic Switching Blocks | NoC Fabrics | Test Time Evaluations |

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