27 search results - page 2 / 6 » Methodologies for Tolerating Cell and Interconnect Faults in... |
FPL
2006
Springer
13 years 9 months ago
2006
Springer
As manufacturing technology enters the ultra-deep submicron era, wafer yields are destined to drop due to higher occurrence of physical defects on the die. This paper proposes a y...
FPGA
2000
ACM
13 years 9 months ago
2000
ACM
In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain ...
CAL
2004
13 years 5 months ago
2004
In this paper we present a methodology to design fault-tolerant routing algorithms for regular direct interconnection networks. It supports fully adaptive routing, does not degrade...
IOLTS
2007
IEEE
13 years 11 months ago
2007
IEEE
i To boost logic density and reduce per unit power consumption SRAM-based FPGAs manufacturers adopted nanometric technologies. However, this technology is highly vulnerable to radi...
FPGA
2003
ACM
13 years 10 months ago
2003
ACM
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...