17 search results - page 2 / 4 » Modeling and Evaluation of Substrate Noise Induced by Interc... |
DFT
2008
IEEE
14 years 6 days ago
2008
IEEE
It is widely recognized that device and interconnect fabrics at the nanoscale will be characterized by an increased susceptibility to transient faults. This appears to be intrinsi...
TVLSI
2002
13 years 5 months ago
2002
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
SLIP
2003
ACM
13 years 11 months ago
2003
ACM
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
3DIC
2009
IEEE
14 years 17 days ago
2009
IEEE
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
VLSID
2005
IEEE
14 years 6 months ago
2005
IEEE
In this paper, we present a simple analytical equation for capturing phase errors in 3-stage ring oscillators. The model, based on a simple but useful idealization of the ring osc...