8 search results - page 1 / 2 » Modeling and optimization of low power resonant clock mesh |
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
Abstract—Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described,...
PATMOS
2005
Springer
13 years 10 months ago
2005
Springer
In this paper, we present a low power high temperature 80C51 microcontroller. The low power optimizations are applied at gate and architectural level, by using extensive clock and ...
ASPDAC
2001
ACM
13 years 8 months ago
2001
ACM
Clock-tuning has been classified as important but tough tasks due to the non-convex nature caused by the skew requirements. As a result, all existing mathematical programming appr...
TVLSI
2010
12 years 11 months ago
2010
This paper proposes a low-power high-throughput digital signal processor (DSP) for baseband processing in wireless terminals. It builds on our earlier architecture--Signal processi...
SECON
2007
IEEE
2007
IEEE
Experimental Investigation of IEEE 802.15.4 Transmission Power Control and Interference Minimization
13 years 11 months ago
Abstract—Although the characteristics of RF transmissions are physically well understood at the lowest levels of communication design, accurately incorporating power and interfer...