9 search results - page 1 / 2 » Modeling the Overshooting Effect for CMOS Inverter in Nanome... |
TCAD
2010
13 years 3 months ago
2010
—With the scaling of complementary metal–oxide– semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacit...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
ISLPED
2009
ACM
13 years 11 months ago
2009
ACM
In this paper, we observe that minimum energy Emin of subthreshold logic dramatically increases when reaching 45 nm node. We demonstrate by circuit simulation and analytical model...
ISCAS
1999
IEEE
13 years 9 months ago
1999
IEEE
A method for modeling complex CMOS gates by the reduction of each gate to an effective equivalent inverter is introduced. The conducting and parasitic behavior of parallel and ser...
DT
2007
13 years 4 months ago
2007
This paper proposes a new heuristic approach to determine the input pattern that minimizes leakage currents of nanometer CMOS circuits during sleep mode considering stack and fano...