14 search results - page 1 / 3 » Multi-layer parallel decoding algorithm and vlsi architectur... |
SIPS
2006
IEEE
13 years 10 months ago
2006
IEEE
Abstract— In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization effi...
ISCAS
2011
IEEE
12 years 8 months ago
2011
IEEE
—We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered de...
ICC
2007
IEEE
13 years 11 months ago
2007
IEEE
— We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard. The proposed architecture utilizes the value–reuse property of offs...
VLSID
2006
IEEE
13 years 10 months ago
2006
IEEE
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...
SIPS
2007
IEEE
13 years 11 months ago
2007
IEEE
Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...