41 search results - page 3 / 9 » Multi-voltage floorplan design with optimal voltage assignme... |
ISLPED
2003
ACM
13 years 11 months ago
2003
ACM
We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous a...
ASPDAC
2005
ACM
13 years 11 months ago
2005
ACM
– Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study ...
ICCD
2005
IEEE
14 years 2 months ago
2005
IEEE
As technology scales, power consumption and thermal effects have become challenges for system-on-chip designers. The rising on-chip temperatures can have negative impacts on SoC p...
ISPD
2009
ACM
14 years 16 days ago
2009
ACM
Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven h...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
Computational complexity has been the primary challenge of many VLSI CAD applications. The emerging multicore and manycore microprocessors have the potential to offer scalable perf...