4 search results - page 1 / 1 » Multilevel full-chip routing with testability and yield enha... |
SLIP
2005
ACM
13 years 10 months ago
2005
ACM
We propose in this paper a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two ...
TCAD
2008
13 years 4 months ago
2008
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, ...
ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pat...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Circuit fabrics composed of highly regular structures, called logic bricks, have been described recently for improving yield. An automated logic brick design flow based on a SAT ...