234 search results - page 2 / 47 » Multiple Faults: Modeling, Simulation and Test |
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
We consider the problem of testing for delay faults in macrobased circuits. Macro-based circuits are obtained as a result of technology mapping. Gate-level fault models cannot be ...
DFT
2003
IEEE
13 years 10 months ago
2003
IEEE
Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this ...
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
common use is the distinction into two (abstract) fault models: A new fault modelling scheme for integrated analogue general the "Single Hard Fault Model (SHFM)" and the ...
DFT
2002
IEEE
13 years 9 months ago
2002
IEEE
1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...
ANSS
2001
IEEE
13 years 8 months ago
2001
IEEE
In this paper, we employ the finite state machine (FSM) model for networks to investigate fault identification using passive testing. First, we introduce the concept of passive te...