17 search results - page 2 / 4 » NBTI tolerant microarchitecture design in the presence of pr... |
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock ...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
TVLSI
2010
13 years 17 hour ago
2010
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...