67 search results - page 2 / 14 » Network on chip design and optimization using specialized in... |
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
Performance models for Network-on-Chip (NoC) are essential for design, optimization and Quality of Service (QoS) assurance. Classical queueing theory has been often used to provid...
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
In this paper, a novel automatic approach for the concurrent topology and routing optimization that achieves a high quality network layout is proposed. This optimization is based ...
MICRO
2010
IEEE
13 years 2 months ago
2010
IEEE
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...