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ICCAD
2009
IEEE
113views Hardware» more  ICCAD 2009»
9 years 2 days ago
A performance analytical model for Network-on-Chip with constant service time routers
Performance models for Network-on-Chip (NoC) are essential for design, optimization and Quality of Service (QoS) assurance. Classical queueing theory has been often used to provid...
Nikita Nikitin, Jordi Cortadella
ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
9 years 7 months ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic
DAC
2005
ACM
10 years 3 months ago
A low latency router supporting adaptivity for on-chip interconnects
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
Jongman Kim, Dongkook Park, Theo Theocharides, Nar...
DAC
2008
ACM
10 years 3 months ago
Concurrent topology and routing optimization in automotive network integration
In this paper, a novel automatic approach for the concurrent topology and routing optimization that achieves a high quality network layout is proposed. This optimization is based ...
Bardo Lang, Christian Haubelt, Jürgen Teich, ...
EUROGP
2004
Springer
170views Optimization» more  EUROGP 2004»
9 years 6 months ago
Comparing Hybrid Systems to Design and Optimize Artificial Neural Networks
Abstract. In this paper we conduct a comparative study between hybrid methods to optimize multilayer perceptrons: a model that optimizes the architecture and initial weights of mul...
Pedro A. Castillo Valdivieso, Maribel Garcí...
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