36 search results - page 2 / 8 » New Performance-Driven FPGA Routing Algorithms |
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
DAC
1995
ACM
13 years 8 months ago
1995
ACM
We propose a novel optimization scheme that can improve the routing by reducing a newly observed router decaying effect. A pair of greedy-grow algorithms, each emphasizing a diffe...
FPGA
2003
ACM
13 years 10 months ago
2003
ACM
The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently dev...
DAC
1994
ACM
13 years 9 months ago
1994
ACM
- This paper studies the routing problem for a new Field-Programmable Gate Array (FPGA) and Field-Programmable Interconnect Chip (FPIC) routing architecture which improves upon the...
FPGA
2009
ACM
13 years 11 months ago
2009
ACM
In this paper we present SPR, a new architecture-adaptive mapping tool for use with Coarse-Grained Reconfigurable Architectures (CGRAs). It combines a VLIW style scheduler and FP...