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» Noise constraint driven placement for mixed signal designs
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ISCAS
2003
IEEE
71views Hardware» more  ISCAS 2003»
13 years 10 months ago
Noise constraint driven placement for mixed signal designs
William H. Kao, Wenkung K. Chu
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
13 years 8 months ago
Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling
This paper proposes Noise-Direct, a design methodology for power integrity aware floorplanning, using microarchitectural feedback to guide module placement. Stringent power constr...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
DAC
1996
ACM
13 years 9 months ago
Use of Sensitivities and Generalized Substrate Models in Mixed-Signal IC Design
A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced nois...
Paolo Miliozzi, Iasson Vassiliou, Edoardo Charbon,...
GLVLSI
2005
IEEE
120views VLSI» more  GLVLSI 2005»
13 years 10 months ago
3D module placement for congestion and power noise reduction
3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today’s mixed signal system integration. In this wo...
Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh
ISQED
2008
IEEE
66views Hardware» more  ISQED 2008»
13 years 11 months ago
An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign
– As silicon technology scales, we can integrate more and more circuits on a single chip, which means more I/Os are needed in modern designs. The flip-chip technology which was ...
Ming-Fang Lai, Hung-Ming Chen