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ISVLSI
2003
IEEE
86views VLSI» more  ISVLSI 2003»
9 years 7 months ago
Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS
SOI (silicon-on-insulator) technology suffers from a number of floating body effects, most notably parasitic bipolar and history effects. These are influenced by the rapidly incre...
Koushik K. Das, Richard B. Brown
DATE
2009
IEEE
171views Hardware» more  DATE 2009»
9 years 6 months ago
Physically clustered forward body biasing for variability compensation in nanometer CMOS design
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse consequences on design predictability and yield. A number of recent works have...
Ashoka Visweswara Sathanur, Antonio Pullini, Luca ...
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