24 search results - page 1 / 5 » Novel architectures for efficient (m, n) parallel counters |
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
—In this paper, a novel VLSI iterative divider architecture for fast quotient generation that is based on radix-2 non-restoring division is proposed. To speed up the quotient gen...
CORR
2010
Springer
13 years 4 months ago
2010
Springer
Fixed-complexity sphere decoder (FSD) is a recently proposed technique for multiple-input multiple-output (MIMO) detection. It has several outstanding features such as constant thr...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
— Fast addition and multiplication are of paramount importance in many arithmetic circuits and processors. The use of redundant number system for efficient implementation of thes...
IPPS
2007
IEEE
13 years 11 months ago
2007
IEEE
: In this paper, we have proposed a time efficient, energy saving and robust broadcast/multicast protocol for reconfigurable cluster-based sensor network. In our broadcast protocol...