18 search results - page 4 / 4 » Obstacle-avoiding rectilinear Steiner minimum tree construct... |
ISVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
The “chicken-egg” dilemma between VLSI interconnect timing optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as...
GLVLSI
2000
IEEE
13 years 9 months ago
2000
IEEE
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
GECCO
2004
Springer
13 years 10 months ago
2004
Springer
The prize-collecting Steiner tree problem on a graph with edge costs and vertex profits asks for a subtree minimizing the sum of the total cost of all edges in the subtree plus th...