27 search results - page 3 / 6 » On Optimizing Scan Testing Power and Routing Cost in Scan Ch... |
ATS
2004
IEEE
13 years 9 months ago
2004
IEEE
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...
VTS
1996
IEEE
13 years 9 months ago
1996
IEEE
Designing a testable circuit is often a two step process. First, the circuit is designed to conform to the functional specifications. Then, the testability aspects are added. By t...
DAC
2007
ACM
14 years 6 months ago
2007
ACM
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
ATS
2004
IEEE
13 years 9 months ago
2004
IEEE
Conventional serial connection of internal scan chains brings the power and time penalty. A novel parallel core wrapper design (pCWD) approach is presented in this paper for reduc...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
Abstract-- In this paper, a technique that can efficiently reduce peak and average switching activity during test application is proposed. The proposed method does not require any ...