27 search results - page 4 / 6 » On Optimizing Scan Testing Power and Routing Cost in Scan Ch... |
VTS
2006
IEEE
13 years 11 months ago
2006
IEEE
— In this paper, an algorithm for scan vector ordering, PEAKASO, is proposed to minimize the peak temperature during scan testing. Given a circuit with scan and the scan vectors,...
IJAIT
2010
13 years 4 months ago
2010
Many real world industrial applications involve finding a Hamiltonian path with minimum cost. Some instances that belong to this category are transportation routing problem, scan c...
DAC
2005
ACM
13 years 7 months ago
2005
ACM
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
Abstract-- This paper proposes a novel power-aware multifrequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time a...
ICCAD
1995
IEEE
13 years 9 months ago
1995
IEEE
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...