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IPPS
2003
IEEE
13 years 11 months ago
Active Memory Techniques for ccNUMA Multiprocessors
Our recent work on uniprocessor and single-node multiprocessor (SMP) active memory systems uses address remapping techniques in conjunction with extended cache coherence protocols...
Daehyun Kim, Mainak Chaudhuri, Mark Heinrich
ASPLOS
1991
ACM
13 years 9 months ago
Performance Evaluation of Memory Consistency Models for Shared Memory Multiprocessors
The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory ...
Kourosh Gharachorloo, Anoop Gupta, John L. Henness...
ISCAS
2006
IEEE
157views Hardware» more  ISCAS 2006»
14 years 2 days ago
DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs
Abstract— Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection ...
Daewook Kim, Manho Kim, Gerald E. Sobelman
HIPC
1999
Springer
13 years 10 months ago
Process Migration Effects on Memory Performance of Multiprocessor
Abstract. In this work we put into evidence how the memory performance of a WebServer machine may depend on the sharing induced by process migration. We considered a shared-bus sha...
Pierfrancesco Foglia, Roberto Giorgi, Cosimo Anton...
IPPS
2006
IEEE
14 years 2 days ago
A segment-based DSM supporting large shared object space
This paper introduces a software DSM that can extend its shared object space exceeding 4GB in a 32bit commodity cluster environment. This is achieved through the dynamic memory ma...
Benny Wang-Leung Cheung, Cho-Li Wang