38 search results - page 2 / 8 » On Reducing Test Data Volume and Test Application Time for M... |
DAC
2001
ACM
14 years 6 months ago
2001
ACM
DFT
2002
IEEE
13 years 10 months ago
2002
IEEE
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
We present a new test resource partitioning (TRP) technique for reduced pin-count testing of system-on-a-chip (SOC). The proposed technique is based on test data compression and o...
VTS
2000
IEEE
13 years 10 months ago
2000
IEEE
A novel design-for-test (DFT) technique is presented for designing a core with a “virtual scan chain” which looks (to the system integrator) like it is shorter than the real s...
VTS
2005
IEEE
13 years 11 months ago
2005
IEEE
This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consum...