187 search results - page 2 / 38 » On Using Efficient Test Sequences for BIST |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
We present a hybrid BIST approach that extracts the most frequently occurring sequences from deterministic test patterns; these extracted sequences are stored on-chip. We use clus...
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
VLSID
2001
IEEE
14 years 5 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
ATS
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
DFT
2009
IEEE
13 years 8 months ago
2009
IEEE
Optimizing the BIST configuration based on the characteristics of the design under test is a complicated and challenging work for test engineers. Since this problem has multiple o...