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ICCAD
2001
IEEE
111views Hardware» more  ICCAD 2001»
14 years 2 months ago
Congestion Aware Layout Driven Logic Synthesis
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...
Thomas Kutzschebauch, Leon Stok
DAC
2000
ACM
13 years 9 months ago
Watermarking while preserving the critical path
In many modern designs, timing is either a key optimization goal and/or a mandatory constraint. We propose the first intellectual property protection technique using watermarking ...
Seapahn Meguerdichian, Miodrag Potkonjak
ICCAD
2003
IEEE
117views Hardware» more  ICCAD 2003»
14 years 2 months ago
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible...
Saurabh N. Adya, Igor L. Markov, Paul Villarrubia
INTEGRATION
2006
82views more  INTEGRATION 2006»
13 years 5 months ago
On whitespace and stability in physical synthesis
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible ...
Saurabh N. Adya, Igor L. Markov, Paul G. Villarrub...
ICCD
1994
IEEE
142views Hardware» more  ICCD 1994»
13 years 9 months ago
Grammar-Based Optimization of Synthesis Scenarios
Systems for multi-level logic optimization are usually based on a set of specialized, loosely-related transformations which work on a network representation. The sequence of trans...
Andreas Kuehlmann, Lukas P. P. P. van Ginneken