96 search results - page 2 / 20 » On test coverage of path delay faults |
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target pat...
GLVLSI
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. The improved detection of CMO...
DAC
1994
ACM
13 years 9 months ago
1994
ACM
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
IOLTS
2000
IEEE
13 years 9 months ago
2000
IEEE
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...