340 search results - page 68 / 68 » On the Interplay of Parallelization, Program Performance, an... |
HPDC
2000
IEEE
13 years 9 months ago
2000
IEEE
The BaBar experiment at the Stanford Linear Accelerator Center (SLAC) is designed to perform a high precision investigation of the decays of the B-meson produced from electron-pos...
HPCA
2004
IEEE
14 years 5 months ago
2004
IEEE
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...
MICRO
2008
IEEE
13 years 11 months ago
2008
IEEE
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
IEEEPACT
2005
IEEE
13 years 11 months ago
2005
IEEE
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
CF
2005
ACM
13 years 7 months ago
2005
ACM
Modern microprocessor designs continue to obtain impressive performance gains through increasing clock rates and advances in the parallelism obtained via micro-architecture design...