12 search results - page 2 / 3 » Optimal Euler Circuit of Maximum Contiguous Cost |
ISQED
2005
IEEE
13 years 11 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
GLVLSI
2000
IEEE
13 years 9 months ago
2000
IEEE
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
VLSID
2007
IEEE
13 years 11 months ago
2007
IEEE
As the VLSI technology scales towards the nanometer regime, circuit performance is increasingly affected by variations. These variations need to be considered at an early stage in...
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
—In this paper a new ADC architecture of flash type is proposed. This proposed N-bit flash ADC replaces the (2N -1)-toN encoder with two (2N/2 -1)-to-(N/2) encoders to accomplish...
JCO
2011
13 years 9 days ago
2011
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...