Sciweavers

10 search results - page 1 / 2
» Optimal Evaluation Clocking of Self-Resetting Domino Pipelin...
Sort
View
ASPDAC
1999
ACM
101views Hardware» more  ASPDAC 1999»
13 years 9 months ago
Optimal Evaluation Clocking of Self-Resetting Domino Pipelines
We describe a high performance clocking methodology for domino pipelines. Our technique maximizes the clock rate of the circular pipeline (“ring”) while maintaining the ring c...
Kenneth Y. Yun, Ayoob E. Dooply
ARVLSI
1999
IEEE
94views VLSI» more  ARVLSI 1999»
13 years 9 months ago
Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allow...
Ayoob E. Dooply, Kenneth Y. Yun
ISLPED
2004
ACM
123views Hardware» more  ISLPED 2004»
13 years 10 months ago
Improved clock-gating through transparent pipelining
This paper re-examines the well established clocking principles of pipelines. It is observed that clock gating techniques that have long been assumed optimal in reality produce a ...
Hans M. Jacobson
ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
13 years 9 months ago
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays
Microprocessor clock frequency has improved by nearly 40% annually over the past decade. This improvement has been provided, in equal measure, by smaller technologies and deeper p...
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler,...
TCAD
2008
127views more  TCAD 2008»
13 years 4 months ago
Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration
Abstract--Multimedia and DSP applications have several computationally intensive kernels which are often offloaded and accelerated by application-specific hardware. This paper pres...
Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozor...