38 search results - page 3 / 8 » Optimal Transistor Tapering for High-Speed CMOS Circuits |
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
—In this paper we study the effectiveness of two power gating methods – transistor switches and MEMS switches – in reducing the power consumption of a design with a certain t...
SBCCI
2005
ACM
13 years 11 months ago
2005
ACM
In this work the design of radiofrequency CMOS circuit blocks in the 910MHz ISM band, while biasing the MOS transistor in the moderate inversion region, is analyzed. An amplifier ...
VLSID
2001
IEEE
14 years 5 months ago
2001
IEEE
Development of the process technology for dual threshold (dual Vth ) CMOS circuit has opened up the possibility of using it to reduce static power in low voltage high performance ...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
Pass Transistor Logic has attracted more and more interest during last years, since it has proved to be an attractive alternative to static CMOS designs with respect to area, perf...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper first presents an accurate and efficient method of estimating the short circuit energy dissipation and the output transition time of CMOS buffers. Next the paper descri...